例句與造句

1. These advantages make usb popular in pc peripheral bus
   Usb的這些特點,使得usb總線取得廣泛的應用。
2. Local peripheral bus
   局域邊緣總線
3. Local peripheral bus
   局域邊緣總線
4. The research and practice of this dissertation complete the design of a bus bridge module which between the on - chip system bus and the peripheral bus
   本論文的研究與實踐工作完成了一個片上系統(tǒng)總線和外設總線之間的總線橋模塊設計。
5. We can connect peripherals to the bus through the box which is on peripheral bus and in so doing we can realize the control and regulation of the bus
   我們將外總線技術引入可穿戴計算機的硬件接口設計,通過總線上的連接器box將外設掛接在總線上。
6. It's difficult to find peripheral bus in a sentence. 用peripheral bus造句挺難的
7. According to this design , we can use the usb as the peripheral bus of wearable computer , making the connection of equipments to the host computer convenient and rapid
   依照此方案選擇將usb總線作為可穿戴計算機的外總線,實現(xiàn)設備方便、快速地與主機相連。
8. The misc logic module can capture and lock the errors of processor local bus and on - chip peripheral bus . these errors can be shown by light - emitting diode light . the chipscope _ ila core is used for debugging the fpga logic and timing
   而輔助邏輯主要是用來捕獲并鎖定powerpc ~ ( tm ) 405的處理器局部總線( plb )和片上外圍總線( opb )的錯誤,并通過led燈進行顯示。
9. The clb bus is a kind of on - chip system bus which is usually used to connect ips with high speed and high data width . the peripheral bus that conform the pvci standard usually used to connect ips with low speed and low data width
   Clb總線是一種片上系統(tǒng)總線，一般用來連接高速度、高數(shù)據(jù)寬度的ip 。而符合pvci標準的外設總線上連接的往往是低速度、低數(shù)據(jù)寬度的ip 。
10. It can communicate with powerpc ~ ( tm ) 405 and control the peripheral equipment of on - chip peripheral bus 。 the b3g test platform not only provides test method of b3g project , but also uses for high - speed data transmission . for example , the b3g test platform may get the data of simulation using fpga
    B3g測試平臺不僅為b3g項目提供了一種調試手段,也可以應用到其它高速數(shù)據(jù)捕獲和傳輸?shù)膱龊?如采用fpga對復雜算法進行仿真,其結果的輸出等) 。
11. The peripheral equipment , which includes serial control , b3g test tools , ddr control , interrupt control , connect the on - chip peripheral bus of powerpc ~ ( tm ) 405 . in addition , the clock module and the misc logic module are necessarily to make the b3g test platform work . in order to debug the b3g test platform , the chipscope ~ ( tm ) core is adopted
    在powerpc ~ ( tm ) 405的外圍總線上開發(fā)了串口控制器、 b3g測試工具、雙倍數(shù)據(jù)流( ddr )內存控制器、中斷控制器等外設;整個系統(tǒng)還需要時鐘、輔助邏輯等模塊;為了方便b3g測試平臺的調試,將chipscope ~ ( tm )核也嵌入到了平臺中。